One type of power MOSFET transistor is a vertically diffused MOS (VDMOS) transistor. Such a power MOSFET transistor is described in U.S. Pat. No. 4,631,564 to J. M. S. Neilson et al, issued Dec. 23, 1986, entitled GATE SHIELD STRUCTURE FOR POWER MOS DEVICE. As shown in FIG. 1, a VDMOS transistor 10 basically comprises a substrate 12 of a semiconductor material of one conductivity type, such as N-type, having first and second opposed major surfaces 14 and 16. Disposed across the second major surface 16 is a relatively high conductivity region 18 of the one conductivity type, such as N+ type, referred to as the drain region. Contiguous with the N+ type drain region 18 is an N- type extended drain region 20 which extends to the first major surface 14.
Extending into the substrate 12 from the first surface 14 are a plurality of lightly doped body regions 22 of the opposite conductivity type, such as P- type. At the first surface 14, each of the body regions 22 is in the form of a hexagon. Extending into the substrate 12 from the first surface 14 within the boundary of each of the body regions 22 is a source region 24 of the one conductivity type, such as N+ type. At the first surface 14, each of the source regions 24 is also hexagonal with the edge of each source region 24 being spaced from the edge of its respective body region 22 so as to define the length and width of a channel region 26 at the first surface 14. Each of the source regions 24 is annular in shape and a P+ type supplementary body region 28 extends into the body region 22 within the source region 24 to a depth which is typically greater than that of the body region 22.
Disposed on the first surface 14 over the channel regions 26 is an insulated gate electrode which comprises gate insulation 30 on the surface 14 and a gate electrode 32 on the gate insulation 30. The gate insulation 30 is typically comprised of silicon dioxide in the thickness range of approximately 500 to 2,000 angstroms, and the gate electrode 32 typically comprises doped polycrystalline silicon. An insulating layer 34, typically comprising a silicate glass, overlies the gate electrode 32 so as to electrically isolate the electrode from overlying layers. A source electrode 36 overlies the insulating layer 34 and contacts the first surface 14 so as to contact the source regions and supplementary body regions. A drain electrode 38 contacts the high conductivity region 18 on the second surface 16. External electrical contact to the gate electrode 32 is made by a gate bond pad 40 which typically comprises a metal.
For certain applications of power MOSFET transistors, it is desirable to protect the transistor against direct shorts across the load or loads of the power supply. For this purpose, current limiting circuits have been used with the power MOSFET. FIG. 2 shows one circuit which has been used for this purpose. The circuit comprises a zener diode D1 across the gate and source terminals of the circuit. A bipolar transistor Q1 has its collector connected to the gate of the power MOSFET Q2 and its emitter connected to the source terminal of the circuit. The base of the bipolar transistor Q1 is also connected to the source of the MOSFET Q2. A current sensing resistor Rlim is connected to the source of the MOSFET Q2, across the base and the emitter of the bipolar transistor Q1 and to the source terminal of the circuit. A resistor R.sub.g is connected between the gate of the MOSFET Q2 and the gate terminal of the circuit to allow the switching speed of the device to be tailored by changing the input rc network time constant. The diode D2 is a parasitic diode built into the MOSFET Q2.
In the operation of this current limiting circuit, the zener diode D1 is used to protect the power MOSFET from electrostatic discharge. Current limiting is obtained when the load current in the power MOSFET Q2 is large enough (i.e. under a shorted load condition) so that the voltage across the limiting resistor Rlim is enough to provide a voltage across the base-emitter junction of the bipolar transistor Q1 which will turn on transistor Q1. When transistor Q1 is turned on, the gate voltage of the power MOSFET Q2 is pulled down through bipolar transistor Q1 and the load current is limited. However, a problem with this current limiting circuit is that the power across the current limiting resistor Rlim can become very high causing the resistor to heat up and adversely affect the operation of the circuit.
Therefore, it would be desirable to have a current limiting circuit for the power MOSFET in which the power dissipation across the power limiting resistor is lowered considerably. Also, it is desirable to have a current limiting circuit for a power MOSFET which can be integrated into the power MOSFET and can be constructed using the same method for making the power MOSFET.